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8-BIT SINGLE CHIP MICROCOMPUTERS
GMS810 SERIES
USERS MANUAL
* GMS81004 * GMS81008 * GMS81016 * GMS81024 * GMS81032
Revision 3.0 Published by MCU Application Team in HYUNDAI ELCETRONICS Co., Ltd. I HYUNDAI ELECTRONICS Co., Ltd. 1998 All Right Reserved.
Additional information of this manual may be served by HYUNDAI ELECTIONICS Offices in Korea or Distributors and Representative listed at address directory. HYUNDAI ELECTIONICS reserves the right to make changes to any Information here in at any time without notice. The information, diagrams, and other data in this manual are correct and reliable; however, HYUNDAI ELECTIONICS Co., Ltd. is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
Table of Contents
Table of Contents
Chapter 1
Overview 1.1 Features & Pin Assignments . . . . . . . . . . . . . . . . . . . . . 1.2 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Package Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Pin Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5 Port Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1-2 1-3 1-5 1-6 1-10
Chapter 2
Function Description 2.1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 TCALL Vector Area . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Zero-Page Peripheral Registers . . . . . . . . . . . . . . . . . . . 2-1 2-6 2-7 2-8
Chapter 3
I/O PORT 3.1 Port R0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Port R1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 Port R2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3-2 3-2
Chapter 4
Peripheral Hardware 4.1 Clock Generating Circuit . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4-10
Table of Contents
Chapter 5
Interrupt 5.1 Interrupt Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Interrupt Accept Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.4 Interrupt Processing Sequence . . . . . . . . . . . . . . . . . . . . 5.5 Software Interrupt . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6 Multiple Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7 Key Scan Input Processing . . . . . . . . . . . . . . . . . . . . . . . 5-1 5-3 5-4 5-7 5-8 5-9 5-11
Chapter 6
Standby Function 6.1 Stop Mode ............................ ..... 6.2 Standby Mode Release . . . . . . . . . . . . . . . . . . . . . . . . . 6.3 Release Operation of Standby Mode . . . . . . . . . . . . . . . 6-1 6-3 6-5
Chapter 7
Reset Function 7.1 External RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Low Voltage Detection Mode . . . . . . . . . . . . . . . . . . . . . 7-1 7-1 7-4
Appendix
Instruction Set Table Programmers guide Mask option list
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Chapter 1. Overview
CHAPTER 1. OVERVIEW
The GMS810 Series is the high speed and Low voltage operating 8-bit single chip microcomputers. This MCU contains G8MC core, ROM, RAM, input/output ports and five multi-function timer/counters.
1.1 FEATURES & PIN ASSIGNMENTS (TOP VIEW)
a
a a a
a a a a
a a a
a
ROM size . . . . . . . . . . . . . 4,096 Bytes ( GMS81004 ) , 8,192 Bytes (GMS81008 ) . . . . . . . . . . . . . 16,384 Bytes ( GMS81016 ) ,24,576 Bytes(GMS81024 ) . . . . . . . . . . . . . 32,768 Bytes ( GMS81032 ) RAM size . . . . . . . . . . . . . 448 Bytes Instruction Execution Time . . 1us @Xin=4MHz Timer U Timer/Counter . . . . . . 8Bit * 2ch , 16Bit * 1ch U Basic Interval Time . . . 8Bit * 1ch U Watch Dog Timer . . . . 6Bit * 1ch Power On Reset Power Saving Operation Modes U STOP 8 Interrupt Sources U Nested Interrupt Control is Available Operating Voltage U 2.0~4.0V @2MHz U 2.2~4.0V @4MHz Low Voltage Detection Circuit Watch dog Timer Auto Start ( During 1Second after Power on Reset ) Package U 20SOP/20PDIP/24SOP/24Skinny DIP/28SOP/28Skinny DIP U 44PLCC I/O Port
input output I/O
20pin 3 2 13
24pin 3 2 17
28pin 3 2 21
44pin 3 2 24
1- 1
Chapter 1. Overview
PIN ASSIGNMENT
R13 R12 R11 R10 VDD XOUT XIN R00 R01 R02 R03 R20 R21 R22
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23
R14 R15 R16 R17 REMOUT RESET TEST R07 R06 R05 R04 VSS R24 R23
R13 R12 R11 R10 VDD XOUT XIN R00 R01 R02 R03 R20
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20
R14 R15 R16 R17 REMOUT RESET TEST R07 R06 R05 R04 VSS R11 R10 VDD XOUT XIN R00 R01 R02 R03 R20
1 2 3 4 5 6 7 8 9 10 20 19 18 17
R16 R17 REMOUT RESET TEST R07 R06 R05 R04 VSS
24PIN
24PIN
19 18 17 16 15 14 13
28PIN
22 21 20 19 18 17 16 15
20PIN
16 15 14 13 12 11
REMOUT
RESET
TEST
VSS
R07
R06
31
R05
30
R27
NC
NC
39
38
37
36
35
34
33
32
NC R17 R16 R15 R14 NC R13 R12 R11 R10 NC
29
NC
40 41 42 43 44 1 2 3 4 5 6
28 27 26 25 24
NC R04 VSS R24 R23 NC R22 R21 R20 R03 NC
44PLCC
23 22 21 20 19 18
10
11
12
13
14
15
16
XOUT
VDD
R01
R00
R02
XIN
R25
R26
NC
1- 2
NC
NC
17
7
8
9
Chapter 1. Overview
1.2 Block Diagram
WATCHDOG TIMER
G8MC CORE
R0 R00~R07 REMOUT R17/T0 R16/T1 R15/T2 R14/EC PORT RAM TIMER (448byte)
R12/INT2 INTERRUPT R11/INT1
R1 R10~R17 PORT
ROM Key scan INT. generation Block (16K byte)
R00~R07 R10~R17
R2 TEST RESET Xin Xout CLOCK GEN. / SYSTEM CONTROL PRESCALER / B.I.T R20~R27 PORT
Vdd
Vss
1- 3
Chapter 1. Overview
1.3 Package Dimension
1.3.1 20SOP Pin Dimension(dimensions in inch)
1.3.2 20PDIP Pin Dimension (dimensions in inch)
1- 4
Chapter 1. Overview
1.3.3 24SOP Pin Dimension (dimensions in inch)
1.3.4 24skinnyDIP Pin Dimension (dimensions in inch)
1- 5
Chapter 1. Overview
1.3.5 28SOP Pin Dimension (dimensions in inch)
1.3.6 28skinnyDIP Pin Dimension (dimensions in inch)
1- 6
Chapter 1. Overview 1.3.7 44PLCC Pin Dimension (dimensions in mm)
1- 7
Chapter 1. Overview
1.4 Pin Function
PIN NAME R00 R01 R02 R03 R04 R05 R06 R07 R10 R11/INT1 R12/INT2 R13 R14/EC R15/T2 R16/T1 R17/T0 R20 R21 R22 R23 R24 R25 R26 R27 XIN XOUT REMOUT RESET TEST VDD VSS VSS
INPUT INPUT/ OUTPUT 20Pin 24Pin 28Pin 44Pin I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O O I I P P P
6 7 8 9 12 13 14 15 2 1 20 19 10 5 4 18 17 16 3 11 8 9 10 11 14 15 16 17 4 3 2 1 24 23 22 21 12 7 6 20 19 18 5 13 8 9 10 11 18 19 20 21 4 3 2 1 28 27 26 25 12 13 14 15 16 7 6 24 23 22 5 17 11 15 16 19 27 30 31 32 5 4 3 2 44 43 42 41 20 21 22 24 25 13 14 36 10 9 38 37 33 8 26 35
Function - Each bit of the port can be individually configured as an input or an output by user software - Push-pull output - CMOS input with pull-up resistor (option) - Can be programmable as Key Scan Input - Pull-ups are automatically disabled at output mode - CMOS input with pull-up resistor (option) - Push-pull output - Can be programmable as Key Scan Input or Open drain output - Direct Driving of LED(N-TR) - Pull-ups are disabled at output mode - CMOS input with pull-up resistor (option) - Push-pull output - Direct Driving of LED(N-TR) - Pull-ups are disabled at output mode
@ RESET @ STOP
INPUT
State of before STOP
INPUT
State of before STOP
INPUT
State of before STOP
- Oscillator Input - Oscillator Output - High Current Output - Includes pull-up resistor - Includes pull-up resistor - Positive power supply - Ground
Low High L output L Output state L level of before STOP
1- 8
Chapter 1. Overview
1.5 Port Structure
1.5.1 R0 PORT
PIN CIRCUIT TYPE VDD Data Reg R00 R01 R02 R03 R04 R05 R06 R07 VDD pull-up option PAD Direction Reg Data Bus e Rd Data Bus e Rd @ RESET
Hi - Z OR High-Input (with pullup)
MUX
VSS
1- 9
Chapter 1. Overview 1.5.2 R1 PORT
PIN open drain selection Data Reg CIRCUIT TYPE VDD VDD pull-up option PAD R10 R11/INT1 R12/INT2 R13 R14/EC Direction Reg Hi - Z OR High-Input (with pullup) @ RESET
Data Bus
MUX
VSS
T0 R11...INT1 T0 R12...INT2 T0 R14...EC open drain selection from R15...T2 from R16...T1 from R17...T0 Data Reg R15 / T2 R16 / T1 R17 / T0 MUX
Rd
VDD
VDD pull-up option PAD Hi - Z OR High-Input (with pullup)
Direction Reg
Data Bus
MUX
VSS
Rd
1 - 10
Chapter 1. Overview 1.5.3 R2 PORT
PIN
CIRCUIT TYPE VDD VDD pull-up option PAD Direction Reg
@ RESET
R20 R21 R22 R23 R24 R25 R26 R27
Data Reg
Hi - Z OR High-Input (with pullup)
Data Bus e Rd
MUX
VSS
REMOUT PORT
PIN CIRCUIT TYPE VDD @ RESET
REMOUT
internal signal
PAD
Low level
VSS
1 - 11
Chapter 1. Overview 1.5.4 Miscellaneous Ports
PIN Xout Xin Xin Xout oscillation CIRCUIT TYPE @ RESET
from STOP circuit VSS VDD pull-up resistor VSS RESET PAD from POWER on RESET circuit VSS VDD TEST PAD pull-up resistor VSS High level Low level
1 - 12
Chapter 1. Overview
1.6 Electrical Characteristics
1.6.1 Absolute Maximum Ratings (Ta = 25E )
PARAMETER Supply Voltage Input Voltage Output Voltage Operating Temperature Storage Temperature 1.6.2 Recommended Operating Ranges Power Dissipation SYMBOL VDD VI VO Topr Tstg PD RATINGS -0.3 ~ +7.0 -0.3 ~ VDD + 0.3 -0.3 ~ VDD + 0.3 0 ~ 70 -65 ~ 150 700 UNIT V V V E E mW
1.6.2 Recommended Operating Ranges
PARAMETER SYMBOL CONDITION fXin = 1MHz fXin = 2MHz fXin = 4MHz MIN. TYP. MAX. UNIT
VDD1 Supply Voltage VDD2 Oscillation Frequency Operating Temperature fXin Topr
2.0
4.0
V
2.2 1.0 0 2.0
4.0 4.0 70
V MHz E
1 - 13
Chapter 1. Overview 1.6.3 DC Characteristics (VDD = 2.0~4.0, Vss = 0V, Ta = 0E ~ 70E )
Specification min 0.8VDD 0.7VDD 0 0 typ max VDD VDD 0.2VDD 0.3VDD 1 -1 VDD-0.4 VDD-0.4 VDD-0.9 VDD-0.9 0.4 0.8 0.8 1 -1 -30 0.5 15 10 -12
-
Parameter high level input voltage low level input voltage high level input leakage current low level input leakage current
Symbol VIH1 VIH2 VIL1 VIL2 IIH IIL VOH1
Condition R11, R12, R14, RESETB R0, R1(Except R11,R12,R14 ) , R2 R11, R12, R14, RESETB R0, R1(Except R11,R12,R14 ) , R2 R0,R1,R2,RESETB R0,R1,R2,RESETB (without pull-up) R0 R1(ExceptR17),R2 R17 OSC R0 R1, R2 OSC R0, R1, R2 R0, R1, R2 REMOUT REMOUT RESETB R0, R1, R2 VIH=VDD VIL=0V IOH=-0.5mA IOH=-1mA IOH=-8mA IOH=-200uA IOL=1mA IOL=5mA IOL=200uA VOH=VDD VOL=0V VOH=2V VOL=1V VDD=3V VDD=3V fXIN=4MHz VDD=4V VDD=2.2V VDD=4V VDD=2V VDD=4V VDD=2V
Unit V V V V uA uA V V V V V V V uA uA mA mA uA uA mA mA mA mA uA uA V
high level output voltage
VOH2 VOH3 VOH5 VOL1
low level output voltage high level output leakage current low level output leakage current high level output current low level output current input pull-up current
VOL2 VOL5 IOHL IOLL IOH IOL IP1 IP2
-5 3 60 40 10 6 6 3 10 8
30 20 4 2.4 2.4 1.2
POWER SUPPLY CURRENT
IDD
operating current fXIN=2MHz stop mode current oscillator stop
ISTOP RAM retention supply voltage VRET
----0.7
3 2
1 - 14
Chapter 1. Overview U GMS810 Series REMOUT port IOH Characteristics graph
0.0
-5.0 VDD=2V -10.0
-15.0 IOH(mA) VDD=3V -20.0
-25.0
-30.0 VDD=4V -35.0
0 1 2 3 4
VOH(V)
U GMS810 Series REMOUT port IOL Characteristics graph
8.00
7.00 VDD=4V 6.00
5.00 IOL(mA)
4.00 VDD=3V 3.00
2.00
1.00
VDD=2V
0.00
0 1 2 3 4
VOL(V)
1 - 15
Chapter 1. Overview
1.6.4 AC Characteristics (VDD = 2.0~4.0, Vss = 0V, Ta = 0E ~ 70E )
Specification No 1 2 3 4 5 6 7 8 9 10 11 12 13 Parameter External clock input cycle time System clock cycle time External clock pulse width High External clock pulse width Low External clock rising time External clock falling time interrupt pulse width High Interrupt pulse width Low Reset input pulse width low Event counter width high Event counter width low Event counter rising time Event counter falling time input pulse input pulse input pulse input pulse Symbol tcp tsys tcpH tcpL trcp tfcp tIH tIL tRSTL tECH tECL trEC tfEC Xin Xin Xin Xin INT1~INT2 INT1~INT2 RESET EC EC EC EC 2 2 8 2 2 40 40 Xin Pin min 250 500 40 40 40 40 typ 500 max 1000 ns ns ns ns ns ns tsys tsys tsys tsys tsys ns ns Unit
1000 2000
* Refer to Fig 1-1
1 - 16
Chapter 1. Overview
tCP
tCPH
tCPL Vcc-0.5V
Xin
trCP tIH tfCP tIL 0.8Vcc
0.5V
INT1 INT2
0.2Vcc tRSTL
RESET
0.2Vcc
tECH
tECL 0.8Vcc 0.2Vcc
EC
0.8Vcc
trEC
tfEC
* FIG-1 : Clock, INT, RESET. EC input timing
1 - 17
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Chapter 2. Function Description
CHAPTER 2. FUNCTION DESCRIPTION
2.1 REGISTERS
15 7 0
PCH
7
PCL
0
Program Counter
A
15 7
A-Register
0
e
YA (16bit Accumulator)
7 0
X
7 0
X-Register
Y
7 0
Y-Register
SP
7 0
Stack Pointer O1
PSW
Program Status Word
e
N V G B H I Z C Carry Flag Zero Flag Interrupt Enable Flag Half Carry Flag Break Flag G Flag Overflow Flag Negative Flag O1 Stack Address
15 7 0
PCH
PCL
e
Fixed as 01XXh (=RAM 1page)
e
SP 2- 1
Chapter 2. Function Description 2.1.1 A register - 8bit Accumulator. - In the case of 16-bit operation, compose the lower 8-bit of A, upper 8bit in Y (16-bit Accumulator) - In the case of multiplication instruction, execute as a multiplier register. After multiplication operation, the lower 8-bit of the result enters. (Y*A ae YA) - In the case of division instruction, execute as the lower 8-bit of dividend. After division operation, quotient enters. 2.1.2 X register - General-purpose 8-bit register - In the case of index addressing mode within direct page(RAM area), execute as index register. - In the case of division instruction, execute as register. 2.1.3 Y register - General-purpose 8-bit register - In the case of index addressing mode, execute as index register - In the case of 16-bit operation instruction, execute as the upper 8-bit of YA (16-bit accumulator). - In the case of multiplication instruction, execute as a multiplicand register. After multiplication operation, the upper 8-bit of the result enters. - In the case of division instruction, execute as the upper 8-bit of dividend. After division operation, remains enters. - Can be used as loop counter of conditional branch command. (e.g.DBNE Y, rel) 2.1.4 Stack Pointer - In the cases of subroutine call, Interrupt and PUSH, POP, RETI, RET instruction, stack data on RAM or in the case of returning, assign the storage location having stacked data. - Stack area is constrained within 1-page (00H-FFH). The SP is post-decremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted; and the SP is pre-incremented when a return or a pop instruction is executed. - SP should be initialized as follows ex) LDX #0FEH : 0FEH ae X reg. TXSP : X reg. ae SP - The behaviors of stack pointer according to each instruction are the following.
2- 2
Chapter 2. Function Description 2.1.4.1 Interrupt
M(SP) c (PCH)
M(SP) c (PCL)
M(SP) c (PSW)
SP c SP - 1
SP c SP - 1
SP c SP - 1
2.1.4.2 RETI( Return from interrupt )
SP c SP + 1
SP c SP + 1
SP c SP + 1
(PSW) c M(SP)
(PCL) c M(SP)
(PCH) c M(SP)
2.1.4.3 Subroutine call
M(SP) c (PCH)
M(SP) c (PCL)
SP c SP - 1
SP c SP - 1
2.1.4.4 RET(Return from subroutine)
SP c SP + 1
SP c SP + 1
(PCL) c M(SP)
(PCH) c M(SP)
2- 3
Chapter 2. Function Description 2.1.4.5 PUSH A(X, Y, PSW)
M(SP) c A
SP c SP - 1
2.1.4.6 POP A(X, Y, PSW)
SP c SP + 1
A c M(SP)
2.1.5 PC (Program Counter) - Program counter is a 16-bit counter consisted of 8-bit register PCH and PCL. - Addressing space is 64K bytes. 2.1.6 PSW (Program Status Word) - PSW is an 8-bit register. - Consisted of the flags showing the post state of operation and the flags determining the CPU operation, initialized as 00H in reset state. 2.1.7 Flag register. 2.1.7.1 Carry flag (C) After operation, set when there is a carry from bit7 of ALU or there is not a borrow. Set by SETC and clear by CLRC. Executable as 1-bit accumulator. Branch condition flag of BCS, BCC.
2.1.7.2 Zero flag (Z) - After operation also including 16-bit operatiion, set if the result is E0E - Branch condition flag of BEQ, BNE. 2.1.7.3 Interrupt enable flag (I) - Master enable flag of interrupt except for RST (reset). - Set and cleared by EI, DI
2- 4
Chapter 2. Function Description 2.1.7.4 Half carry flag (H) - After operation, set when there is a carry from bit3 of ALU or there is not a borrow from bit4 of ALU. - Can not be set by any instruction. - Cleared by CLRV instruction like V flag. 2.1.7.5 Break flag (B) - Set by BRK (S/W interrupt) instruction to distinguish BRK and TCALL instruction having the same vector address. 2.1.7.6 G flag (G) - Set and cleared by SETG, CLRG instruction. - Assign direct page (0-page, 1-page). - Addressable directly to RAM 1-page by SETG. and to RAM 0-page by CLRG. 2.1.7.7 Overflow flag (V) - After operation, set when overflow or underflow occurs. - In the case of BIT instruction, bit6 memory location is transferred to V-flag. - Cleared by CLRV instruction, but not set by any instruction. - Branch condition flag of BVS, BVC. 2.1.7.8 Negative flag (N) - Set whenever the result of a data transfer or operation is negative (bit7 is set to E1E). - In the case of BIT instruction, bit7 of memory location is transferred to N-flag - N-flag is not affected by CLR or SET instruction. - Branch condition flag of BPL, BMI.
2- 5
Chapter 2. Function Description
2.2 MEMORY MAP
0000h RAM (192 BYTES) 00BFh PERIPHERAL REGISTERS 0100h RAM (STACK) (256 BYTES) 0200h NON-USE 8000h ROM (32,768 BYTES) A000h GMS81024 GMS81032 1-PAGE DIRECT PAGE
0-PAGE
ROM (24,576 BYTES) C000h ROM (16,384 BYTES) E000h ROM (8,192 BYTES) F000h ROM (4,096 BYTES) FF00h PCALL AREA FFC0h TCALL VECTOR AREA FFE0h INTERRUPT VECTOR AREA FFFFh U-PAGE GMS81004 GMS81008 GMS81016 PROGRAM ROM
2- 6
Chapter 2. Function Description
2.3 TCALL VECTOR AREA
FFC0h FFC1h FFC2h FFC3h FFC4h FFC5h FFC6h FFC7h FFC8h FFC9h FFCAh FFCBh FFCCh FFCDh FFCEh FFCFh FFD0h FFD1h FFD2h FFD3h FFD4h FFD5h FFD6h FFD7h FFD8h FFD9h FFDAh FFDBh FFDCh FFDDh FFDEh FFDFh (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H) (L) (H)
TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0
*
* This
vector area is used in BRK command and TCALL0 command.
2- 7
Chapter 2. Function Description
2.4 ZERO-PAGE PERIPHERAL REGISTERS
RESET VALUE ADDRESS
00C0H 00C1H 00C2H 00C3H 00C4H 00C5H 00C6H 00C7H 00C8H 00C9H 00CAH 00CBH 00CCH 00CDH 00CEH 00CFH 00D0H 00D1H 00D2H 00D3H 00D4H 00D5H
FUNCTION REGISTERS
PORT R0 DATA REG. PORT R0 DATA DIRECTION REG. PORT R1 DATA REG. PORT R1 DATA DIRECTION REG. PORT R2 DATA REG. PORT R2 DATA DIRECTION REG. Reserved CLOCK CONTROL REG. BASIC INTERVAL REG. WATCH DOG TIMER REG. PORT R1 MODE REG. INT. MODE REG. EXT. INT. EDGE SELECTION INT. ENABLE REG. HIGH INT. REQUEST FLAG REG. LOW INT. ENABLE REG. HIGH INT. REQUEST FLAG REG. HIGH TIMER 0 (16bit) MODE REG. TIMER 1 (8bit) MODE REG. TIMER 2 (8bit) MODE REG. TIMER 0 HIGH-MSB DATA REG. TIMER 0 HIGH-LSB DATA REG. TIMER0 LOW-MSB DATA REG. TIMER0 LOW-MSB COUNT REG. TIMER0 LOW-LSB DATA REG. TIMER0 LOW-LSB COUNT REG. TIMER 1 HIGH DATA REG. TIMER1 LOW DATA REG. TIMER1 LOW COUNT REG. TIMER2 DATA REG. TIMER2 COUNT REG. TIMER 0/ TIMER1 MODE REG. Reserved STANDBY MODE RELEASE REG0 STANDBY MODE RELEASE REG1 PORT R1 OPEN DRAIN ASSIGN REG.
R/W
R/W W R/W W R/W W
SYMBOL 76543210
R0 R0DD R1 R1DD R2 R2DD Undefined 00 Undefined 00 Undefined 00
W R W W R/W W R/W R/W R/W R/W R/W R/W R/W W W W R W R W W R W R R/W
CKCTLR BITR WDTR PMR1 IMOD IEDS IENL IRQL IENH IRQH TM0 TM1 TM2 T0HMD T0HLD T0LMD
-
-
1
1
0
1
1
1
Undefined 0 0 0 00 0 0 00 0 0 0 0 0 0 0 0 0 0 00 00 00 Undefined Undefined Undefined Undefined 0 0 0 0 0 0 0 0 0 0 1 1 1 1
00D6H 00D7H 00D8H
T0LLD
Undefined Undefined
T1HD T1LD
Undefined Undefined Undefined
00D9H 00DAH 00DBH 00DCH 00DDH 00DEH
T2DR
Undefined Undefined
TM01
00
W W W
SMRR0 SMRR1 R1ODC
00 00 00
- ; Not used * Caution : Write only register can not be accessed by bit manipulation instruction. : Do not access the Reserved registers .
2- 8
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Chapter 3. I/O PORT
CHAPTER 3. I/O PORTS
The GMS810series has 21 I/O ports which are PORT0(8 I/O), PORT1 (8 I/O) and PORT2 (8 I/O). Each port contains data direction register which controls I/O and data register which stores port data.
3.1 PORT R0
3.1.1 PORT R0 Registers
REGISTER
R0 I/O Data Direction Register R0 Data Register
SYMBOL
R0DD R0
R/W
W R/W
RESET VALUE
00H Undefined
ADDRESS
00C1H 00C0H
Table 3.1 Port R0 Registers
3.1.2 I/O Data Direction Register (R0DD)
bit R0DD initial value R/W 7 R0DD7 0 W 6 R0DD6 0 W 5 R0DD5 0 W 4 R0DD4 0 W 3 R0DD3 0 W 2 R0DD2 0 W 1 R0DD1 0 W 0 R0DD0 0 W <00C1H>
R0 I/O Data Direction Register(R0DD) is 8-bit register, and can assign input state or output state to each bit. If R0DD is E1E, port R0 is in the output state, and if E0E, it is in the input state. R0DD is write-only register. Since R0DD is initialized as E00HE in reset state, the whole port R0 becomes input state. 3.1.1 Data Register(R0)
bit R0 initial value R/W 7 R07 X R/W 6 R06 X R/W 5 R05 X R/W 4 R04 X R/W 3 R03 X R/W 2 R02 X R/W 1 R01 X R/W 0 R00 X R/W <00C0H>
PORT0 data register (R0) is 8-bit register to store data of port R0. When setted as the output state by R0DD, and data is written in R0, data is outputted into R0 pin. When set as the input state, input state of pin is read. The initial value of R0 is unknown in reset state.
3 -1
Chapter 3. I/O PORT
3.2 PORT R1
PIN NAME
R10 R11/INT1 R12/INT2 R13 R14/EC R15/T2 R16/T1 R17/T0
PORT SELECTION
R10(I/O) R11(I/O) R12(I/O) R13(I/O) R14(I/O) R15(I/O) R16(I/O) R17(I/O)
FUNCTION SELECTION
INT1 (INPUT) INT2 (INPUT) EC (INPUT) T2 (OUTPUT) T1 (OUTPUT) T0 (OUTPUT)
Fig 3.1 Pin Function of port R1
3.2.1 PORT R1 Register
REGISTER
R1 I/O Data Direction Register R1 Data Register R1 Port Mode Register R1 Port Open drain Assign Register
SYMBOL
R1DD R1 PMR1 R10DC
R/W
W R/W W W
RESET VALUE
00H Undefined 00H 00H
ADDRESS
00C3H 00C2H 00C9H 00CEH
Table 3.1 Port R1 Registers
3.2.2 I/O Data Direction Register (R1DD)
bit R1DD initial value R/W 7 R1DD7 0 W 6 R1DD6 0 W 5 R1DD5 0 W 4 R1DD4 0 W 3 R1DD3 0 W 2 R1DD2 0 W 1 R1DD1 0 W 0 R1DD0 0 W <00C3H>
R1 Data Direction Register(R1DD) is 8-bit register, and can assign input state or output state to each bit. If R1DD is E1E, port R1 is in the output state, and if E0E, it is in the input state. R1DD is write-only register. Since R1DD is initialized as E00HE in reset state, the whole port R1 becomes input state.
3 -2
Chapter 3. I/O PORT 3.2.3 Data Register(R1) R1 Data Register(R1) is 8-bit register to store data of port R1. When set as the output state by R1DD, and data is written in R1, data is output into R1 pin. The initial value of R1 is unknown in reset state.
bit R1 initial value R/W 7 R17 X R/W 6 R16 X R/W 5 R15 X R/W 4 R14 X R/W 3 R13 X R/W 2 R12 X R/W 1 R11 X R/W 0 R10 X R/W <00C2H>
3.2.4 Port R1 Open drain Assign Register (R1ODC)
bit R1ODC initial value R/W 7 R17OD 0 W 6 R16OD 0 W 5 R15OD 0 W 4 R14OD 0 W 3 R13OD 0 W 2 R12OD 0 W 1 R11OD 0 W 0 R10OD 0 W <00DEH>
Port R1 Open Drain Assign Register(R1ODC) is 8bit register, and can assign R1 port as open drain output port each bit, if corresponding port is selected as output. If R1ODC is selected as E1E, port R1 is open drain output, and if selected asE0E, it is push-pull output. R1ODC is write-only register and initialized as E00HE in reset state.
3 -3
Chapter 3. I/O PORT 3.2.5 Port R1 Mode Register (PMR1)
bit PMR1 initial value R/W 7 T0S 0 W 6 T1S 0 W 5 T2S 0 W 4 ECS 0 W 3 0 W 2 INT2S 0 W 1 INT1S 0 W 0 0 W <00C9H>
R1 Port Mode Register(PMR1) is 8-bit register, and can assign the selection mode for each bit. When set asE0E, corresponding bit of PMR1 acts as port R1 selection mode, and when set asE1E, it becomes function selection mode.
BIT NAME
T0S
PMR1
0 1 0 1 0 1 0 1 0 1 0 1 0 1
Selection Mode
R17 Sel(I/O) T0 Sel (Output) R16 Sel (I/O) T1 Sel (Output) R15 Sel (I/O) T2 Sel (Output) R14 Sel (I/O) EC Sel (Input) -
Remarks
Output Port of Timer0 Output Port of Timer1 Output Port of Timer2 Input Port of Timer0 Event Input
T1S
T2S
ECS
-
INT2S
R12 sel (I/O) INT2 Sel (Input) R11 Sel (I/O) INT1 Sel (Input)
Input Port of Timer0 Input capture -
INT1S
-
Table 3.3 Selection Mode of PMR1
PMR1 is write-only register and initialized as E 00HE in reset state. Therefore, becomes Port selection mode. Port R1 can be I/O port by manipulating each R1DD bit, if corresponding PMR1 bit is selected as E0E.
3 -4
Chapter 3. I/O PORT
3.3 PORT R2
3.3.1 PORT R2 Registers
REGISTERS
R2 I/O Data Direction Register R2 Data Register
SYMBOL
R2DD R2
R/W
W R/W
RESET VALUE
00H Undefined
ADDRESS
00C5H 00C4H
Table 3.3 Port R2 Registers
3.3.2 I/O Data Direction Register (R2DD)
bit R2DD initial value R/W 7 R2DD7 0 W 6 R2DD6 0 W 5 R2DD5 0 W 4 R2DD4 0 W 3 R2DD3 0 W 2 R2DD2 0 W 1 R2DD1 0 W 0 R2DD0 0 W <00C5H>
R2 Data Direction Register(R2DD) is 8-bit register, and can assign input state or output state or output state to each bit. If R2DD is E1E, port R2 is in the output state, and if E0E, it is in the input state. R2DD is write-only register. Since R2DD is initialized as E00HE in reset state, the whole port R2 becomes input state. 3.3.3 Data Register (R2)
bit R2 initial value R/W 7 R27 X R/W 6 R26 X R/W 5 R25 X R/W 4 R24 X R/W 3 R23 X R/W 2 R22 X R/W 1 R21 X R/W 0 R20 X R/W <00C4H>
R2 Data Register(R2) is 8-bit register to store data of port R2. When setted as the output state by R2DD, and data is written in R2, data is output into R2 pin. When setted as input state, input state of pin is read. The initial value of R2 is unknown in reset state.
3 -5
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Chapter 4. Peripheral Hardware
CHAPTER 4. PERIPHERAL HARDWARE
4.1 CLOCK GENERATING CIRCUIT
Clock generating circuit consists of Clock Pulse Generator(C.P.G), Prescaler, Basic Interval Timer(B.I.T) and Watch Dog Timer. The clock applied to the Xin pin divided by two is used as the internal system clock.
fex OSC Circuit C.P.G
fcpu
Internal System Clock
PRESCALER IFBIT PS1 ENPCK 8 MUX B.I.T (8) WDT (6) 9 0 7 0 5 WDTCL
BTCL IFWDT 3 Peripheral COMPARATOR WDTON 6 0 CKCTLR 0 1 2 3 4 5 WDTR 6 5 6 To Reset Circuit
Internal Data Bus
Fig. 4.1 Block diagram of clock generating circuit
4 -1
Chapter 4. Peripheral Hardware 4.1.1 Oscillation Circuit Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Fig. 4.2-(a) shows circuit diagrams using a crystal (or ceramic) oscillator. As shown in the diagram, oscillation circuits can be constructed by connecting a oscillator between Xout and Xin. Clock from oscillation circuit makes CPU clock via clock pulse generator, and then enters prescaler to make peripheral hardware clock. alternately, the oscillator may be driven from an external source as shown is Fig. 4.2.(b). In the Standby(STOP) mode, oscillatiion stop, Xout state goes to EHIGHE, Xin state goes to ELOWE, and built-in feed back resistor is disabled. (a) External Crystal (Ceramic) oscillator circuit
Cout Xout
Xin Cin
(b) External clock input circuit
Xout
Xin
External clock
Fig. 4.2 Oscillator configurations
*. Recommendable resonator
Frequency Resonator Maker
CQ KYOCERA 4.0MHz KYOCERA TDK TDK TDK
Part Name
ZTA4.00MG KBR- 4.0MKC KBR- 4.0MSB FCR4.0MC5 FCR4.0M5 CCR4.0MC3
Load Capacitor
Cin=Cout=30pF Cin=Cout=open Cin=Cout=33pF Cin=Cout=open Cin=Cout=33pF Cin=Cout=open
Operating Voltage
2.2 ~ 4.0V 2.2 ~ 4.0V 2.2 ~ 4.0V 2.2 ~ 4.0V 2.2 ~ 4.0V 2.2 ~ 4.0V
O MC type is building in load capacitior.CCR type is chip type.
4 -2
Chapter 4. Peripheral Hardware 4.1.2 Prescaler Prescaler consists of 12-bit binary counter. The clock supplied from oscillation circuit is input to prescaler (fex). The divided output from each bit of prescaler is provided to peripheral hardware. 4.1.3 Peripheral hardware clock control Clock to peripheral hardware can be stopped by bit4 (ENPCK) of CKCTLR Register. ENPCK is set to E1E in reset state.
fex
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
PS11
PS12
ENPCK
B.I.T fcpu PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 Peripheral
fex(MHz) Freq 4 Period(s) Freq 2 Period(s)
PS0
4M
PS1
2M
PS2
1M
PS3
500K
PS4
250K
PS5
125K
PS6
62.5K
PS7
31.25K
PS8
15.63K
PS9
7.183K
PS10
3.906K
PS11
1.953K
PS12
0.976K
250n
2M
500n
1M
1u
500k
2u
250K
4u
125K
8u
62.5K
16u
31.25K
32u
15.63K
64u
7.183K
128u
3.906K
256u
1.953K
512u 1024u
0.976K 0.488K
500n
1u
2u
4u
8u
16u
32u
64u
128u
256u
512u 1024u 2048u
Fig. 4.3 Block diagram of Prescaler
4 -3
Chapter 4. Peripheral Hardware
Clock Control Register
7 CKCTLR WDTON ENPCK BTCL BTS2 BTS1 0 BTS0 W <00C7H>
ENPCK
0 1
Peripheral Clock
Stopped Provided
4.1.4 Basic Interval Timer (B.I.T) - 8bit binary counter - Use the bit output of prescaler as input to secure the oscillation stabilization time after power-on - Secures the oscillation stabilization time in standby mode (stop mode) release - Contents of B.I.T can be read - Provides the clock for watch dog timer.
DATA BUS WTON ENPCK BTCL BTS2 BTS1 BTS0
CKCTLR
PS3 PS4 PS5 PS6 MUX PS7 PS8 PS9 PS10 DATA BUS BIT0 BIT1 BIT2 BIT3 BIT4 BIT5 BIT6
BITR BIT7 IFBIT
Fig. 4.4 Block diagram of Basic Interval Timer
4 -4
Chapter 4. Peripheral Hardware 4.1.4.1 Control of B.I.T If bit3(BTCL) of CKCTLR is set to E1E, B.I.T is cleared, and then, after one machine cycle, BTCL becomes E0E, and B.I.T starts counting. BTCL is set to E0E in reset state.
Clock Control Register
7 CKCTLR WDTON ENPCK BTCL BTS2 BTS1 0 BTS0 W <00C7H>
BTCL
0 1
B.I.T Operation
free-run Automatically cleared, after one cycle
4.1.4.2 Input Clock Selection of Basic Interval Timer The input clock of B.I.T can be selected from the prescaler within a range of 2us to 256us by clock input selection bits(BTS2~BTS0). (at fex = 4MHz). In reset state, or power on reset, BTS2=1, BTS1=1, BTS0=1 to secure the longest oscillation stabilization time. B.I.T can generate the wide range of basic interval time interrupt request(IFBIT) by selecting prescaler output. Interrupt interval can be selected to 8 kinds of interval time as shown in Table. 4.1.
4 -5
Chapter 4. Peripheral Hardware
7 CKCTLR WDTON ENPCK BTCL BTS2 BTS1
0 BTS0 W <00C7H>
BTS2
0 0 0 0 1 1 1 1
BTS1
0 0 1 1 0 0 1 1
BTS0
0 1 0 1 0 1 0 1
B.I.T. Input clock
PS3 (2us) PS4 (4us) PS5 (8us) PS6 (16us) PS7 (32us) PS8 (64us) PS9 (128us) PS10 (256us)
Standby release time
512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us
Table 4.1 Standby release time according to BTS
4.1.4.3 Reading Basic Interval Timer By reading of the Basic Interval Timer Register(BITR), we can read counter value of B.I.T. Because B.I.T can be cleared or read, the spending time up to maximum 65.5ms can be available. B.I.T is read-only register. If B.I.T register is written, then CKCTLR register with same address is written.
Basic Interval Timer Register
7 BITR BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 0 BIT0 R <00C7H>
4 -6
Chapter 4. Peripheral Hardware 4.1.5 Watch Dog Timer Watch Dog Timer(WDT) consists of 6-bit binary counter, 6-bit comparator, and Watch Dog Timer Register (WDTR).
0 IFBIT WDT0 WDT1 WDT2 WDT3 WDT4 WDT5 To Reset circuit 5 CLR WDTON
6BIT COMPARATOR
IF WDT 0 WDTR WDTR0 WDTR1 WDTR2 WDTR3 WDTR4 WDTR5 6 WDTCL W <00C8H>
Internal Data Bus
Fig. 4.5 Block diagram of Watch Dog Timer
4.1.5.1 Control of WDT Watch Dog Timer can be used 6-bit general Timer or specific Watch dog timer by setting bit5(WDTON) of Clock Control Register(CKCTLR).
Clock Control Register
7 CKCTLR WDTON ENPCK BTCL BTS2 BTS1 0 BTS0 W <00C7H>
WDTON
0 1
Watch Dog Timer Function Control
6-bit Timer Watch Dog Timer
4 -7
Chapter 4. Peripheral Hardware
By assigning bit6(WDTCL) of WDTR, 6-bit counter can be cleared
Watch Dog Timer Register
7 WDTR WDTCL WDTR5 WDTR4 WDTR3 WDTR2 WDTR1 0 WDTR0 W <00C8H>
Determine Interval of IFWDT Interval of IFWDT = Value of WDTR Interval of IFBIT
WDTCL
0 1
Watch Dog Timer Operation
Free-run Automatically cleared, after one machine cycle
(Caution) : after WDTCL = 1, timer maximum error is one cycle of IFBIT.
4.1.5.2 WDT Interrupt Interval WDT Interrupt(IFWDT) interval is determined by the interrupt IFBIT interval of Basic Interval Timer and the value of WDT Register. Interval of IFWDT = (IFBIT interval) * (WDTR value) Interval of IFWDT : 512us 1 = 512us (MIN>) : 65,536us 63 = 4,128,768us (MAX>) As IFBIT (Basic Interval Timer Interrupt Request) is used for input clock of WDT, Input clock cycle is possible from 512us to 65,536us by BTS. (at fex = 4MHz) *At Hardware reset time ,WDT starts automatically.Therefore, the user must select the CKCTLR,WDTR before WDT overflow. ( Reset WDTR value = 0Fh,15 interval of WDT = 65,536 15 = 983040 uS (about 1second ) )
4 -8
Chapter 4. Peripheral Hardware
7 CKCTLR WDTON ENPCK BTCL BTS2 BTS1
0 BTS0 W <00C7H>
BTS2
0 0 0 0 1 1 1 1
BTS1
0 0 1 1 0 0 1 1
BTS0
0 1 0 1 0 1 0 1
Input clock of WDT
512 us 1,024 us 2,048 us 4,096 us 8,192 us 16,384 us 32,768 us 65,536 us
Max. Interval of WDT output (*note1)
32,756 us 64,512 us 129,024 us 258,048 us 516,096 us 1,032,192 us 2,064,384 us 4,128,768 us
*note1) When WDTR Register value is 63(3FH) Caution : Do not use E0E for WDTR Register value. Device come into the reset state by WDT
4 -9
Chapter 4. Peripheral Hardware
4.2 TIMER
4.2.1 Timer operation mode
Timer consists of 16bit binary counter Timer0(T0), 8bit binary Timer1(T1), Timer2(T2), Timer Data Register, Timer Mode Register (TM01, TM0, TM1, TM2) and control circuit. Timer Data Register Consists of Timer0 High-MSB Data Register(T0HMD), Timer0 HighLSB Data Register(T0HLD), Timer0 Low-MSB Data Register(T0LMD), Timer0 Low-LSB Data Register(T0LLD), Timer1 High Data Register(T1HD), Timer1 Low Data Register(T1LD), Timer2 Data Register(T2DR). Any of the PS0~PS5, PS11 and external event input EC can be selected as clock source for T0. Any of the PS0~PS3, PS7~PS10 can be selected as clock T1. Any of the PS5~PS12 can be selected as clock source for T2.
16-bit Interval Timer 16-bit Event Counter - Single/Modulo-N Mode 16-bit Input Capture - Timer Output Initial Value Setting 16-bit rectangular-wave output - Timer0~Timer1 combination Logic Output - One Interrupt Generating Every 2nd Counter Overflow - 8-bit Interval Timer -8-bit rectangular-wave output - 8-bit Interval Timer -8-bit rectangular-wave output - Modulo-N Mode -
Timer0
Timer1
Timer2
*Relevant Port Mode Register (PMR1 : 00C9H) value should be assigned for event counter, rectangular-wave output and input capture mode.
4 - 10
Chapter 4. Peripheral Hardware
EC/R14
TIMER0 (16 BIT)
Polarity Selection
T0 OUT/R17
INT2/R12 (Capture Signal)
EDGE Selection
16
16
8 T0HMD T0HLD
8
8 T0LMD T0LLD
8
Tout LOGIC T1 HD T1 LD
REMOUT
8 TIMER1 (8 BIT)
8 T1 OUT/R16
T2DR
TIMER2 (8 BIT)
T2 OUT/R15
Fig. 4.6 Timer/Counter Block diagram
4 - 11
Chapter 4. Peripheral Hardware
4.2.2 Function of Timer & Counter
fex = 4MHz
16bit Timer (T0)
Resolution (CK) PS0 PS1 PS2 PS3 PS4 PS5 ( 0.25us) ( 0. 5us) ( ( ( ( 1us) 2us) 4us) 8us) MAX.Count 16,384us 32,768us 65,536us 131,072us 262,144us 524,288us 33,554,432us -
8bit Timer (T1)
Resolution (CK) PS0 PS1 PS2 PS3 PS7 PS8 PS9 (0,.25us) ( 0,5us) ( ( ( ( 1us) 2us) 32us) 64us) MAX.Count 64us 128us 256us 512us 8,192us 16,384us 32,768us 65,536us
8bit Timer (T2)
Resolution (CK) PS5 PS6 PS7 PS8 PS9 ( ( ( ( 8us) 16us) 32us) 64us) MAX.Count 2.048us 4,096us 8,192us 16,384us 32,768us 65,536us 131,072us 262,144us
( 128us)
PS10 ( 256us) PS11 ( 512us) PS12 (1,024us)
PS11 (512us) EC
( 128us)
PS10 (256us)
4 - 12
Chapter 4. Peripheral Hardware
Internal Data Bus
R/W
<00D0H> TM0 7 6 5 4 3 2 1 0
<00D5H>
<00D6H>
<00D3H> <00D4H> TIMER0 HM DATA REG TIMER0 HL DATA REG
<00D5H> TIMER0 LM DATA REG
<00D6H>
TIMER0 H COUNT REG
TIMER0 L COUNT REG
TIMER0 LL DATA REG
DATA READ
SINGLE/ MODULO-N SELECTION
16
16
MUX
16
PS0 PS1 PS2 PS3 PS4 PS5 PS11 EC D E L A INT2 EDGE SELECTION Y M U X MUX CK Int. Gen. T0 COUNTER (16 BIT) IFT0 Clear
T0INT OUTPUT GEN.
T0 OUT
Fig. 4.7 Block Diagram of Timer0
4 - 13
Chapter 4. Peripheral Hardware
Timer0 mode Register
7 TM0 CAP0 T0ST T0CN T0MOD T0IFS T0SL2 T0SL1 0 T0SL0 R/W <00D0H>
T0SL2
0 0 0 0 1 1 1 1
T0SL1
0 0 1 1 0 0 1 1
T0SL0
0 1 0 1 0 1 0 1
Input Clock Sel.
PS0 PS1 PS2 PS3 PS4 PS5 PS11 EC (250ns) (500ns) ( 1us) ( 2us) ( 4us) ( 8us) (512us)
Notes
*
Event Counter
T0IFS
0 1
Timer0 Interrupt Sel.
Interrupt Every Counter Overflow Interrupt Every 2nd Counter Overflow
T0MOD
0 1
Timer0 Single / Modulo-N Sel.
Modulo-N Single Mode
T0CN
0 1
Timer0 Counter Continuation / Pause Control
Count Pause Count Continuation
T0ST
0 1
Timer0 Start/Stop control
Timer0 Stop Timer0 Start after Clear
CAP0
0 1 Timer/Counter Input Capture*
Timer0 Interrupt Sel.
*PS1 : not supporting input capture.
4 - 14
Chapter 4. Peripheral Hardware
Internal Data Bus <00D8H> <00D1H> TM1 7 6 5 4 3 X 2 1 0 R/W TIMER1 COUNT REG TIMER1 H DATA REG TIMER1 L DATA REG <00D7H> <00D8H>
SINGLE/ MODULO-N SELECTION
OUTPUT GEN.
PS0 PS1 PS2 PS3 PS7 PS8 PS9 PS10 IFT1 MUX CK T1 COUNTER (8 BIT) Int. Gen.
T1INT
OUTPUT GEN.
T1OUT
Fig. 4.8 Block Diagram of Timer1
4 - 15
Chapter 4. Peripheral Hardware
Timer1 mode Register
7 TM1 T1ST T1CN T1MOD T1IFS T1SL2 T1SL1 0 T1SL0 R/W <00D1H>
T1SL2
0 0 0 0 1 1 1 1
T1SL1
0 0 1 1 0 0 1 1
T1SL0
0 1 0 1 0 1 0 1
Input Clock Sel.
PS0 PS1 PS2 PS3 PS7 PS8 PS9 PS10 (250ns) (500ns) ( 1us) ( 2us) ( 32us) ( 64us) (128us) (256us)
T1IFS
0 1
Timer1 Interrupt Sel.
Interrupt Every Counter Overflow Interrupt Every 2nd Counter Overflow
T1MOD
0 1
Timer1 Single / Modulo-N Sel.
Modulo-N Single Mode
T1CN
0 1
Timer1 Countern Continuation / Pause Control
Count Pause Count Continuation
T1ST
0 1
Timer1 Start/Stop control
Timer1 Stop Timer1 Start after Clear
4 - 16
Chapter 4. Peripheral Hardware
Timer0/Timer1 mode Register
7 TM01 TOUTS TOUTB T0OUTP T0INIT T1INIT TOUT1 0 TPIT0 R/W <00DAH>
T0UT1
0 0 1 1
T0UT0
0 1 0 1
TOUT LOGIC
AND of T0 OUTPUT and T1 OUTPUT NAND of T0 OUTPUT and T1 OUTPUT OR of T0 OUTPUT and T1 OUTPUT NOR of T0 OUTPUT and T1 OUTPUT
T1INIT
0 1
Timer1 Output Initial Value
Timer1 Output Low Timer1 Output HIgh
T0INIT
0 1
Timer0 Output Initial Value
Timer0 Output Low Timer0 Output High
T0OUTP
0 1
T0OUTPolarity Selection
T0OUT Polarity Equal to TOUT Logic Input Signal T0OUT Polarity Reverse to TOUT Logic Input Signal
TOUTB
0 1
REMOUT Port Bit Control
REMOUT Output Low REMOUT Output High
TOUTS
0 1
REMOUT Port Output Selection (TOUT Logic or TOUTB)
Bit(TOUTB) Output Through REMOUT TOUT Logic Output Through REMOUT
4 - 17
Chapter 4. Peripheral Hardware
Internal Data Bus <00D9H> <00D2H> TM2 7 6 5 4 3 2 1 0 R/W TIMER2 COUNT REG TIMER2 DATA REG <00D9H>
PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 MUX CK T2 COUNTER (8 BIT) IFT2
OUTPUT GEN.
T2 OUT
Fig. 4.9 Block Diagram of Timer2
4 - 18
Chapter 4. Peripheral Hardware
Timer2 mode Register
7 TM2 T2ST T2CN T2SL2 T2SL1 0 T2SL0 R/W <00D2H>
T2SL2
0 0 0 0 1 1 1 1
T2SL1
0 0 1 1 0 0 1 1
T2SL0
0 1 0 1 0 1 0 1
Input Clock Sel.
PS5 PS6 PS7 PS8 PS9 PS10 PS11 PS12 ( 8us) ( 16us) ( 32us) ( 64us) ( 128us) ( 256us) ( 512us) (1,024us)
T2cn
0 1
Timer2 Counter Continuation / Pause Control
Count Pause Count Continuation
T2ST
0 1
Timer2 Start / Stop Control
Timer2 Stop Timer2 Start after Clear
4 - 19
Chapter 4. Peripheral Hardware
PORT mode Register1
7 PMR1 T0S T1S T2S ECS INT2S INT1S 0 W <00C9H>
PMR1
0 T0S 1 0 T1S 1 0 T2S 1 0 ECS 1 0 INT2S 1 0 INT1S 1 -
PORT Sel.
R17 (I/O) T0 (Output) R16 (I/O) T1 (Output) R15 (I/O) T2 (Output) R14 (I/O) EC (Input) R12 (I/O) INT2 (Input) R11 (I/O) INT1 (Input) -
Remarks
Output Port of Timer0 Output Port of Timer1 Output Port of Timer2 Input Port of Timer0 Event -
Input Port of Timer0 Input Capture -
External Interrupt Signal Edge Selectin Register
7 IEDS IED2H IED2L IED1H IED1L 0 W <00CBH>
IED*H
0 0 1 1
IED*L
0 1 0 1
INT*
-FallingEdge Selection Rising Edge Selection Both Edge Selection
4 - 20
Chapter 4. Peripheral Hardware
4.2.3 Timer0, Timer1 TIMER0 and TIMER1 have an up-counter. When value of the up-counter reaches the content of Timer Data Register(TDR), the up-counter is cleared to E00HE, and interrupt(IFT0, IFT1) is occured at the next clock
Fig. 4. 10 Operatiion of Timer0
Concurrence T0 Data Registers Value T0 Value Concurrence Concurrence
0 CLEAR INTERRUPT CLEAR INTERRUPT CLEAR INTERRUPT
IFT0 Interval period
For Timer0, the internal clock(PS) and the external clock(EC) can be selected as counter clock. But Timer1 and Timer2 use only internal clock. As internal clock. Timer0 can be used as internal-timer which period is determined by Timer Data Register(TDR). Chosen as external clock, Timer0 executes as event-counter. The counter execution of Timer0 and Timer1 is controlled by T0CN, T0ST, CAP0, T1CN, T1ST, of Timer Mode Register TM0 and TM1. T0CN, T1CN are used to stop and start Timer0 and Timer1 without clearing the counter. T0ST, T1ST is used to clear the counter. For clearing and starting the counter, T0ST or T1ST should be temporarily set to E0E and then set to E1E. T0CN, T1CN, T0ST and T1ST should be set E1E, when Timer counting-up. Controlling of CAP0 enables Timer0 as input capture. By programming of CAP0 to E1E, the period of signal from INT2 can be measured and then, event counter value for INT2 can be read.
4 - 21
Chapter 4. Peripheral Hardware
T0 Data Register Value T0 Value
Concurrence
Concurrence
0
CLEAR INTERRUPT
CLEAR INTERRUPT
IFT0 0 1 Clear & Start
T0ST
T0CN
0
1
Counter Stop Count Clear & Count Stop Count Clear & Start continue
Fig. 4. 11. Start/Stop operation of Timer0
T3
T2
T1 T0
INT0
Fig. 4. 12. Input capture operation of Timer0
4 - 22
Chapter 4. Peripheral Hardware During counting-up, value of counter can be read. Timer execution is stopped by the reset signal (RESET = ELE) (Note) in the process of reading 16-bit Timer Data, first read the upper 8-bit data. Then read the lower 8-bit data, and read the upper 8-bit data again. If the earlier read upper 8-bit data are matched with the later read upper 8-bit data, read 16-bit data are correct. If not, caution should be taken in the selection of upper 8-bit data. Example) 1) Upper 2) Lower 3) Upper 8-bit 8-bit 8-bit Read Read Read 0A FF 0B 0A 01 0B
e e
0AFF 0B01
4.2.3.1 Single/Modulo-N Mode Timer0 (Timer1) can select initial (T0INIT, T1INIT of TM0, TM1) output level of Timer Output port. If initial level is ELE, Low-Data Register value of Timer Data Register is transferred to comparator and T0OUT(T1OUT) is to be ELowE, if initial level is EHighE, High -Data Register is transferred and to be EHighE. Single Mode can be set by Mode Select bit(T0MOD, T1MOD) of Timer Mode Register (TM0, TM1) to E1E When used as Single Mode, Timer counts up and compares with value of Data Register. If the result is same, Time Out interrupt occurs and level of Timer Output port toggle, then counter stops as reset state. When used as Modulo-N Mode, T0MOD(T1MOD) should be set E0E. Counter counts up until the value of Data Register and occurs Time-out interrupt. The level of Timer Output port toggle and repeats process of counting the value which is selected in Data Register. During Modulo-N Mode, If interrupt select bit(T0IFS, T1IFS) of Mode Register is E0E, Interrupt occurs on every Time-out. If it is E1E, Interrupt occurs every second time-out. (*note. Timer Output is toggled whenever time out happen)
4 - 23
Chapter 4. Peripheral Hardware
8bit / 16bit counting
Timer Enable initial. value toggle.
Timer-output toggle. interrupt occurs. count stop.
< Single Mode >
8bit / 16bit counting
Timer Enable initial. value toggle. Timer-Output Toggle. Int occurs(IFS = 1) Each 2nd time out. Int occurs(IFS = 0) When Time out.
< Modulo-N Mode > Fig. 4. 13 Operation Diagram for Single/Modulo-N Mode
4 - 24
Chapter 4. Peripheral Hardware
4.2.4 Timer2 Timer2 operates as a up-counter. The content of T2DR are compared with the contents of up-counter. If a match is found. Timer2 interrupt (IFT2) is generated and the up-counter is cleared to E00HE. Therefore, Timer2 executes as a interval timer. Interrupt period is determined by the count source clock for the Timer2 and content of T2DR. When T2ST is set to 1, count value of Timer 2 is cleared and starts countingcup. For clearing and starting the Timer2. T2ST have to set to E1E after set to E0E. In order to write a value directly into the T2DR, T2ST should be set to E0E. Count value of Timer2 can be read at any time.
Concurrence T2 Data Registers Value T2 Value Concurrence Concurrence
0 CLEAR INTERRUPT CLEAR INTERRUPT CLEAR INTERRUPT
IFT0 Interval period
Fig. 4. 14 Operation of Timer2
4 - 25
Chapter 4. Peripheral Hardware
Concurrence T2 Data Register Value T2 Value
Concurrence
0
CLEAR INTERRUPT
CLEAR INTERRUPT
IFT2 count stop by 0 count start clear by 1
T2ST
Counter Count up Count Stop Count continue Count up after clear
Fig. 4. 15. Start/Stop of Timer2
4 - 26
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Chapter 5. Interrupt
CHAPTER 5. INTERRUPT
The GMS810 Series contains 8 interrupt sources; 3 externals and 5 internals. Nested interrupt services with priority control is also possible. Software interrupt is nonmaskable interrupt, the others are all maskable interrupts. - 8 interrupt source (2Ext, 3Timer, BIT, WDT and Key Scan) - 8 interrupt vector - Nested interrupt control is possible - Programmable interrupt mode
U
Hardware accept mode Software selection accept mode
U
- Read and write of interrupt request flag are possible. - In interrupt accept, request flag is automatically cleared. Interrupt hardware consists of Interrupt Mode Register(MOD), Interrupt Enable Register High (IENH), Interrupt Enable Register Low(IENL), Interrupt Request Register High(IRQH), Interrupt Request Register Low(IRQL) and priority circuit. Interrupt function block diagram is shown in Fig. 5.1
5.1 INTERRUPT SOURCE
Each interrupt vector is independent and has its own priority. Software interrupt(BRK) is also available. Interrupt source classification is shown in Table 5.1
5 -1
Chapter 5. Interrupt
Internal Data Bus
0 IENL -
7 -
0 IENH -
7
0 IMOD
7 -
KSCN INT1 INT2 IFT0 IFT1 IFT2 IFWDT IFBIT
KSCNR INT1R INT2R T0R T1R T2R WDTR BITR IRQ BRK Standby Mode Release PRIORITY CONTROL INT. VECTOR ADDR.
Fig. 5.1 Interrupt Source
Mask
Non-maskable
Priority
0 1
Interrupt Source
RST (RESET PIN) KSCNR (Key Scan) INT1R(External Interrupt 1) INT2R(External Interrupt 2) T0R (Timer0) T1R (Timer1) T2R (Timer2) WDTR (Watch Dog Timer) BITR (Basic Interval Timer)
INT Vector H INT Vector L
FFFF FFFB FFF9 FFF7 FFF3 FFF1 FFEF FFE9 FFE7 FFFE FFFA FFF8 FFF6 FFF2 FFF0 FFEE FFE8 FFE6
Hardware Interrupt
Maskable
2 3 4 5 6 7
Software Interrupt
-
-
BRK Instruction
FFDF
FFDE
Table 5.1 Interrupt Source
5 -2
Chapter 5. Interrupt
5.2 INTERRUPT CONTROL REGISTER
I flag of PSW is a interrupt mask enable flag. When I flag = E0E, all interrupts become disable. When I flag = E1E, interrupts can be selectively enabled and disabled by contents of corresponding Interrupt Enable Register. When interrupt is occured, interrupt request flag is set, and Interrupt request is detected at the edge of interrupt signal. The accepted interrupt request flag is automatically cleared during interrupt cycle process. The interrupt request flag maintains E1E until the interrupt is accepted or is cleared in program. In reset state, interrupt request flag register(IRQH, IRQL) is cleared to E0E. It is possible to read the state of interrupt register and to mainpulate the contents of register and to generate interrupt. (Refer to software interrupt).
7 IENL WDTR
Interrupt Enable Register Low
BITE -
0 R/W <00CCH>
7 IENH KSCNE INT1E
Interrupt Enable Register High
INT2E T0E T1E T2E
0 R/W <00CEH>
7 IRQL WDTR
Interrupt Request Register Low
BITE -
0 R/W <00CDH>
7 IRQH KSCNR INT1R
Interrupt Request Register High
INT2R T0R T1R T2R
0 R/W <00CFH>
5 -3
Chapter 5. Interrupt
5.3 INTERRUPT ACCEPT MODE
The interrupt priority order is determined by bit(IM1, IM0) of IMOD register.
Interrupt Mode Register
7 IMOD IM1 IM0 IP3 IP2 IP1 0 IP0 R/W <00CAH>
Assigning by interrupt accept mode bit
IM1
0 0 1
IM0
0 1 *
Priority
Fixed by H/W Changeable by IP 3-0 Interrupt is inhibited
5.3.1 Selection of interrupt by IP3 - IP0 The condition allow for accepting interrupt is set state of the interrupt mask enable flag and the interrupt enable bit must be E1E.
IP3
0 0 0 0 0 0 0 1 1 1 1 1
IP2
0 0 0 1 1 1 1 0 0 0 0 1
IP1
0 1 1 0 0 1 1 0 0 1 1 0
IP0
1 0 1 0 1 0 1 0 1 0 1 0
Selection interrupt
KSCNR (Key Scan) INT1R (External interrupt 1) INT2R (External interrupt 2) Reserved T0R (Timer 0) T1R (Timer 1) T2R (Timer 2) Reserved Reserved WDTR (Watch Dog Timer) BITR (Basic Interval Timer) Reserved
Table 5.2 Interrupt Selection by IP3 - IP0
*In Reset state, these IP3 - IP0 registers become all E0E.
5 -4
Chapter 5. Interrupt 5.3.2 Interrupt Timing
CLOCK
A command before interrupt
interrupt process step
SYNC
Interrupt Request Sampling
Fig. 5.2 Interrupt Enable Accept Timing
Interrupt Request sampling time
Maximum 12 machine cycle (When execute DIV instruction) Minimum 0 machine cycle
Interrupt preprocess step is 8 machine cycle Maximum 1 + 12 + 8 = 21 machine cycle Interrupt overhead Minimum 1 + 0 + 8 = 9 machine cycle
5.3.3 The valid timing after executing Interrupt control instructions I flag is valid just after executing of EI/DI on the contrary. Interrupt Enable register is valid one instruction after controlling interrupt Enable Register.
5 -5
Chapter 5. Interrupt
5.4 INTERRUPT PROCESSING SEQUENCE
When an interrupt is accepted, the on-going process is stopped and the interrupt service routine is executed. After the interrupt service routine is completed it is necessary to restore everything to the state before the interrupt occured. As soon as an interrupt is accepted, the content of the program counter and PSW are saved in the stack area. At the same time, the content of the vector address corresponding to the accepted interrupt, which is in the interrupt vector table, enters into the program counter and interrupt service is executed. In order to execute the interrupt service routine, it is necessary to write the jump addresses in the vector table (FFEOH-FFFFH) corresponding to each interrupt
Interrupt Processing Step
1) Store upper byte of Program Counter, SP c SP
2) Store lower byte of Program Counter, SP c SP - 1
3) Store Program Status Word, SP c SP - 2
4) After resetting of I-flag, clear accepted Interrupt Request Flag.(Set B-flag for BRK Instruction)
5) Call Interrupt service routine
5 -6
Chapter 5. Interrupt
Clock Interrupt Process Step SYNC ISR*1
R/W
INTERNAL ADDR. BUS
PC
SP
SP-1
SP-2
LVA*2
HVA*3
NEW PC
INTERNAL DATA BUS
OP CODE
OP CODE
PCH
PCL
PSW
ELE VECTOR
EHE VECTOR
INTERNAL READ
INTERNAL WRITE
Fig. 5. 3 Interrupt Procesing Step Timing *1 ISR : Interrupt Service Routine *2 LVA : Low Vector Address *3 HVA : High Vector Address
5.1 SOFTWARE INTERRUPT
5.5.1 Interrupt by Break(BRK) Instruction Software interrupt is available just by writing EBreak(BRK)E instruction. The values of PC and PSW is stacked by BRK instruction and then B flag of PSW is set and I flag is reset.
Flag change by BRK execution
N V G B H I Z C PSW
set N V G 1 H
reset 0 Z C PSW
(Right after BRK execution)
5 -7
Chapter 5. Interrupt Interrupt vector of BRK instruction is shared by vector of Table Call(TCALL0). When both instruction of BRK and TCALL0 are used, as shown in Fig. 5.4 each processing routine is judged by contents of B flag. There is no instruction to reset directly B flag.
B flag 1 BRK or TCALL0 BRK INTERRUPT ROUTINE
0
TCALL0 ROUTINE
RETI
RET
Fig. 5.4 Execution of BRK or TCALL0
5.6 MULTIPLE INTERRUPT
If there is an interrupt, Interrupt Mask Enable Flag is automatically cleared before entering the Interrupt Service Routine. After then, no interrupt is accepted. If EI instruction is executed, interrupt mask enable bit becomes E1E, and each enable bit can accept interrupt request. When two or more interrupts are generated simultaneously, the highest priority interrupt set by Interrupt Mode Register is accepted.
5 -8
Chapter 5. Interrupt
5.7 Key Scan Input Processing
Key Scan Interrupt is generated by detecting low Input from each Input pin (R0, R1) or standby(SLEEP, STOP) release signal. Key Scan ports are all 16bit which are controlled by Stand-by Mode Release Register (SMRR0, SMRR1). Key Input is considered as Interrupt, therefore, KSCNE bit of IEHN should be set for correct interrupt executing, SLEEP mode and STOP mode, the rest of executing is the same as that of external Interrupt. Each SMRR Register bit is allowed for each port(for Bit=0, no Key Input, for Bit=1, Key Input available). At reset, SMRR becomes E00HE. So, there is no Key Input source.
7 SMRR0 0 W <00DCH>
R00 R01 . . R07 7 SMRR1
R0 port Selection Logic
0 W <00DDH>
Internal Key Scan Interrupt
R10 R11 . . R17
R1 port Selection Logic

5 -9
Chapter 5. Interrupt
SMRR0 Mode Register
7 SMRR0 KR07 KR06 KR05 KR04 KR03 KR02 KR01 0 KR00 W <00DCH>
KR00 0 1
Key Input Selection no select select
KR01 0 1
Key Input Selection no select select
KR02 0 1
Key Input Selection no select select
KR03 0 1
Key Input Selection no select select
KR04 0 1
Key Input Selection no select select
KR05 0 1
Key Input Selection no select select
KR06 0 1
Key Input Selection no select select
KR07 0 1
Key Input Selection no select select
5 - 10
Chapter 5. Interrupt
SMRR1 Mode Register
7 SMRR1 KR17 KR16 KR15 KR14 KR13 KR12 KR11 0 KR10 W <00DDH>
KR10 0 1
Key Input Selection no select select
KR11 0 1
Key Input Selection no select select
KR12 0 1
Key Input Selection no select select
KR13 0 1
Key Input Selection no select select
KR14 0 1
Key Input Selection no select select
KR15 0 1
Key Input Selection no select select
KR16 0 1
Key Input Selection no select select
KR17 0 1
Key Input Selection no select select
5 - 11
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Chapter6. Standby Function
CHAPTER 6. STANDBY FUNCTION
To save power consumption, there is STOP modes. In this modes, the execution of program stops.
6.1 STOP MODE
STOP mode can be entered by STOP instruction during program. In STOP mode, oscillator is stopped to make all clocks stop, which leads to less power consumption. All registers and RAM data are preserved. ENOPE instruction should be follows STOP instruction for rising precharge time of Data Bus line. ex) STOP : STOP instructiion excution NOP : NOP instruction
6 -1
Chapter6. Standby Function
OSC. Circuit
Clock Pulse GEN CLR
CPU Clock
MUX Basic Interval Timer CLR Prescaler CLR B.I.T 7
STOP
S R
Q
S R
Q
Control Signal
Overflow Detection
Release Signal From Interrupt Circuit RESET
Fig. 6.1 Block Diagram of Standby Circuit
Prescaler
ENPCK
PS10
Selector
Basic Interval Timer
Peripheral
Fig. 6.2 ENPCK and Basic Interval Timer Clock
6 -2
Chapter6. Standby Function
6.2 STANDBY MODE RELEASE
6.2.1 STOP Mode Release Release of STANDBY mode is executed by RESET input and Interrupt signal. Register value is defined when Reset. When there is a release signal of STOP mode (Interrupt, RESET input), the instruction execution starts after stabilization oscillation time is set by value of BTS2~BTS0 and set ENPCK to 1.
Table 6.1. Standby Mode Register
Release Signal
RESET KSCN (Key input) INT1 - INT2
STOP
0 0 0
Table 6.2 Standby Mode Release
Release Factor
RESET Pin
Release Method
By RESET Pin = Low level, Standby mode is release and system is initialized Standby mode is released by Low input of selected pin by Key Scan Input (SMRR0, SMRR1) In case of interrupt Mask Enable flag = 0, program executes just after standby instruction, if flag = 1, enters each interrupt service routine. When external interrupt (INT1, INT2) enable flag is E1E, standby mode is released at the rising edge of each terminal. When Standby mode is released at interrupt. Mask Enable flag = 0, program executes from the next instruction of standby instruction. When 1, enters each interrupt service routine.
KSCN (Key input)
INT 1 pin INT 2 pin
6 -3
Chapter6. Standby Function

CLCOK STOP Mode
Stable OSC. time
Release By Interrupt Program Setting Time by CKCTLR Refer to Table 4-1 RESET
Longer than stable OSC. Time
Fig. 6.3 Release Timing of Standby Mode
6.3 RELEASE OPERATION OF STANDBY MODE After Standby mode is released, the operation begins according to content of related interrupt register just before Standby mode start(Fig. 6.3)
6.3.1 In Case of Interrupt Enable Flag(I) of PSW = 0 Release by only interrupt which interrupt enable flag = 1, and starts to execute from next to Standby instruction (STOP).
6 -4
Chapter6. Standby Function 6.3.2 In Case of Interrupt Enable Flag(I) of PSW = 1 Released by only interrupt which each interrupt enable flag = 1, and jump to the relevant interrupt service routine. Note) When STOP instruction is used, B.I.T should guarantee the stabilization oscillation time. Thus, just before entering STOP mode, clock of bit10(PS10) of Prescaler is selected or peripheral hardware clock control bit(ENPCK) to 1, Therefore the clock necessary for stabilization oscillation time should be input into B.I.T. otherwise, Standby mode is released by reset signal. In case of interrupt request flag and interrupt enable flag are both E1E, Standby mode is not entered.
Fig. 6.5 Standby Mode Release Flow
STOP Command
Standby Mode
Interrupt Request GEN.
0 IE Flag 1 Standby Mode Release
PSW IE Flag 1 Interrupt Service Routine
0
Standby Next Command Execution
6 -5
Chapter6. Standby Function
Internal circuit
Oscillator Internal CPU clock Register RAM I/O port Prescaler Basic Interval Timer Watch Dog Timer Timer Address Bus, Data Bus
STOP Mode
Stop Stop Retained Retained Retained Stop Stop Stop Stop Retained
Table 6.3 Operation State in Standby Mode
6 -6
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Chapter7. Reset Function
CHAPTER 7. RESET FUNCTION
7.1 EXTERNAL RESET
The RESET pin should be held at low for at least 2machine cycles with the power supply voltage within the operating voltage range and must be connected 0.1uF capacitor for stable system initialization. The RESET pin contains a Schmitt trigger with an internal pull-up resistor.
RESET
0.1uF capacitor
Fig 7.0 RESET Pin connection.
7.2 POWER ON RESET
Power On Reset circuit automatically detects the rise of power voltage (the rising time should be within 50ms) the power voltage reaches a certain level, RESET terminal is maintained at ELE Level until a crystal ceramic oscillator oscillates stably. After power applies and starting of oscillation, this reset state is maintained for about oscillation cycle of 219 (about 65.5ms : at 4MHz). The execution of built-in Power On Reset circuit is as follows : (1) Latch the pulse from Power On Detection Pulse Generator circuit, and reset Prescaler, B.I.T and B.I.T Overflow detection circuit. (2) Once B.I.T Overflow detection circuit is reset. Then, Prescaler starts to count. (3) Prescaler output is inputted into B.I.T and PS10 of Prescaler output is automatically selected. If overflow of B.I.T is detected, Overflow detection circuit is set. (4) Reset circuit generates maximum period of reset pulse from Prescaler and B.I.T.
7 -1
Chapter7. Reset Function
Internal IC
VDD
RESET 0.1uF
Internal Reset
Power On DET Pulse GEN.
VSS
XTAL OSC.
CLR Prescaler
PS10
CLR Basic Interval Tiemr
MSB
CLR Basic Interval Tiemr
Fig. 7.1 Block Diagram of Power On Reset Circuit
Notice ; When Power On Reset, oscillator stabilization time doesnt include OSC. Start time.
VDD
PRESCALER COUNT START
OSC. START TIMING
Fig. 7.2 Oscillator stabilization diagram
7 -2
Chapter7. Reset Function
RESET
INTERNAL RESET ADDR. BUS SP SP-1 SP-2 FFFE FFFF NEW PC
INTERNAL DATA BUS
FE
LSB MSB VECTOR VECTOR
Fig. 7.3 Reset Timing by Diagram
7 -3
Chapter7. Reset Function
7.3 Low Voltage Detection Mode
7.3.1 Low voltage detection condition An on board voltage comparator checks that VDD is at the required level to ensure correct operation of the device. If VDD is below a certain level, Low voltage detector forces the device into low voltage detection mode. 7.3.2 Low Voltage Detection Mode There is no power consumption except stop current, stop mode release function is disabled. All I/O port is configured as input mode and Data memory is retained until voltage through external capacitor is worn out. In this mode, all port can be selected with Pull-up resistor by Mask option. If there is no information on the Mask option sheet ,the default pull up option (all port connect to pull-up resistor ) is selected. 7.3.3 Release of Low Voltage Detection Mode Reset signal result from new battery(normally 3V) wakes the low voltage detection mode and come into normal reset state. It depends on user whether to execute RAM clear routine or not.
Low Voltage (V)
3.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 0E 10E 20E 30E 40E 50E 60E 70E
Temperature(E)
Fig 7.5 Low Voltage vs Temperature
7 -4
Chapter7. Reset Function
* SRAM BACK-UP after Low Voltage Detection.
3.0V about hours depend on Vcc-Gnd Capacitor
MCU OPR. Voltage Low Voltage Detection point
1.8V(TYP) ( 20E)
Power On Reset ( SRAM retention)
0.7V(VRET) 0V * SRAM Data Backup * The operation after Low voltage detection Interrupt : disable Stop release : disable All I/O port : input Mode Remout port : Low Level OSC : STOP All I/O port pull-up ON (Mask Option ) SRAM Data retention
Power On Reset ( SRAM unstable )
User Removes Batteries
User Replace Batteries
* S/W flow chart example after Reset using SRAM Back-up
RESET Stack Pointer initialize
Check the SRAM value (RAM Pattern, Check sum..)
SRAM DATA IS VALID? Y Use saved SRAM value
N
Clear All Ram area
7 -5
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Appendix A. Instruction Set Table
APPENDIX A. INSTRUCTION SET TABLE
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 ADC ADC ADC ADC ADC ADC ADC ADC AND AND AND AND AND AND AND AND ASL ASL ASL ASL BBC BBC BBS BBS BCC BCS BEQ BIT BIT BMI BNE BPL BRA BRK BVC BVS CLR1 CLRA1 CLRC CLRG CLRV rel rel dp.bit A.bit
MNEMONIC
#imm dp dp+X !abs !abs+Y [dp+X] [dp]+Y {X} #imm dp dp+X !abs !abs+Y [dp+X] [dp]+Y {X} A dp dp+X !abs A.bit, rel dp.bit, rel A.bit, rel dp.bit, rel rel rel rel dp !abs rel rel rel rel
OP CODE Words
04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 y2 y3 x2 x3 50 D0 F0 0C 1C 90 70 10 2F 0F 30 B0 y1 2B 20 40 80 2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 3 2 3 2 2 2 2 3 2 2 2 2 1 2 2 2 2 1 1 1
Exec. Cycle
2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 4/6 5/7 4/6 5/7 2/4 2/4 2/4 4 5 2/4 2/4 2/4 4 8 2/4 2/4 4 2 2 2 2
OPERATION
A = A + op + C E E E E E E E A = A & op E E E E E E E op = op << 1 E E E if (bit = 0) then branch if (bit = 1) then branch if (C=0) branch if (C=1) branch if (Z=1) branch Z = A & op E if (N=1) branch if (Z=0) branch if (N=0) branch Branch S/W interrupt if (V=0) branch if (V=1) branch op.bit = 0 E C=0 G=0 V=0 N N N N N N N N N N N N N N N N N N N N
Flag MVG HIZC
V V V V V V V V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . H H H H H H H H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z C C C C C C C C . . . . . . . . C C C C
........ ........ ........ ........ ........ ........ ........ NN. . . . Z . NN. . . . Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . 1. 0. . ........ ........ ........ ........ .......0 . . 0. . . . . . 0. . 0. . .
A -1
Appendix A. Instruction Set Table
Exec. Cycle
2 3 4 4 5 6 6 3 4 2 3 4 2 3 4 3 3 2 4 5 5 2 2 12 3 3 2 3 4 4 5 6 6 3 2 4 5 5 2 2 3 5 4 8 8 6 8
No.
42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88
MNEMONIC
CMP CMP CMP CMP CMP CMP CMP CMP COM CMPX CMPX CMPX CMPY CMPY CMPY DAA DAS DEC DEC DEC DEC DEC DEC DIV DI EI EOR EOR EOR EOR EOR EOR EOR EOR INC INC INC INC INC INC JMP JMP JMP CALL CALL PCALL TCALL #imm dp dp+X !abs !abs+Y [dp+X] [dp]+Y {X} A dp dp + X !abs X Y !abs [!abs] [dp] !abs [dp] upage n A dp dp + X !abs X Y #imm dp dp+X !abs !abs+Y [dp+X] [dp]+Y {X} dp #imm dp !abs #imm dp !abs
OP CODE Words
44 45 46 47 55 56 57 54 2C 5E 6C 7C 7E 8C 9C DF CF A8 A9 B9 B8 AF BE 9B 60 E0 A4 A5 A6 A7 B5 B6 B7 B4 88 89 99 98 8F 9E 1B 1F 3F 3B 5F 4F nA 2 2 2 3 3 2 2 1 2 2 2 3 2 2 3 1 1 1 2 2 3 1 1 1 1 1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 3 3 2 3 2 2 1
OPERATION
Compare A, op E E E E E E E dp = dp Compare X, op E E Compare Y, op E E E Dec. adjustment (Add) Dec. adjustment (Sub) op = op -1 E E E E E Q:A, R:Y c YA/X I=0 I=1 A = A + op E E E E E E E OP = OP + 1 E E E E E Branch E E Subroutine call E E E N N N N N N N
Flag MVG HIZC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z Z Z Z Z Z C C C C C C C
N. . . . . ZC N. . . . . Z. N. . . . . ZC N. . . . . ZC N. . . . . ZC N. . . . . ZC N. . . . . ZC N. . . . . ZC N. . . . . ZC N. . . . . ZC N N N N N N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z Z Z Z Z C C C C C C
NV. . H. Z. . . . . . 0. . . . . . . 1. . N N N N N N N N N N N N N N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z Z Z Z Z Z Z Z Z Z Z Z Z . . . . . . . . C C C C C C
........ ........ ........ ........ ........ ........ ........
A -2
Appendix A. Instruction Set Table
Exec. Cycle
2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 2 4 5 5 9 2 2 3 4 4 5 6 6 3 4 4 4 4 4 4 4 4 2 4 5 5 2 4 5 5
No.
89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 LDA LDA LDA LDA LDA LDA LDA LDA LDA LDM LDX LDX LDX LDX LDY LDY LDY LDY LSR LSR LSR LSR MUL
MNEMONIC
#imm dp dp+X !abs !abs+Y [dp+X] [dp]+Y {X} {X}+ dp, #imm #imm dp dp+Y !abs #imm dp dp+X !abs A dp dp + X !abs
OP CODE Words
C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 48 49 59 58 5B FF 2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 1 2 2 3 1 1 2 2 2 3 3 2 2 1 1 1 1 1 1 1 1 1 1 2 2 3 1 2 2 3
OPERATION
A = op E E E E E E E A = op, X = X+1 dp = #imm X = op E E E Y = op E E E op = op >>1 E E E YA = Y * A No operation A = A : op E E E E E E E Push op, SP = SP - 1 E E E Pop op, SP = SP + 1 E E E op = op << 1, with C E E E op = op >> 1, with C E E E N N N N N N N N N N N N N N N N N
Flag MVG HIZC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z Z Z Z Z Z Z Z . . . . . . . . .
........ N N N N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z Z Z Z Z Z Z Z Z Z Z . . . . . . . . C C C C
N. . . . . Z. ........ N N N N N N N N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z Z Z Z Z Z Z . . . . . . . . . . . . . . . .
NOP OR OR OR OR OR OR OR OR PUSH PUSH PUSH PUSH POP POP POP POP ROL ROL ROL ROL ROR ROR ROR ROR #imm dp dp+X !abs !abs+Y [dp+X] [dp]+Y {X} A X Y PSW A X Y PSW A dp dp+X !abs A dp dp+X !abs
64 65 66 67 75 76 77 74 0E 2E 4E 6E 0D 2D 4D 6D 28 29 39 38 68 69 79 78
........ ........ ........ (restored) N N N N N N N N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Z Z Z Z Z Z Z Z C C C C C C C C
A -3
Appendix A. Instruction Set Table
Exec. Cycle
6 5 2 3 4 4 5 6 6 3 4 2 2 2 4 5 5 6 7 7 4 4 3 4 5 5 4 5 5 2 2 3 2 2 2 2 4 4 5 5 6 5 4
No.
137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179
MNEMONIC
RETI RET SBC SBC SBC SBC SBC SBC SBC SBC SETI SETA1 SETC SETG STA STA STA STA STA STA STA STA STOP STX STX STX STY STY STY TAX TAY TST TSPX TXA TXSP TYA XAX XAY XCN XMA XMA XMA XYX dp dp+X {X} dp dp dp+Y !abs dp dp+X !abs dp dp+X !abs !abs+Y [dp+X] [dp]+Y {X} {X}+ #imm dp dp+X !abs !abs+Y [dp+X] [dp]+Y {X} dp.bit A.bit
OP CODE Words
7F 6F 24 25 26 27 35 36 37 34 x1 0B A0 C0 E5 E6 E7 F5 F6 F7 F4 FB EF EC ED FC E9 F9 F8 E8 9F 4C AE C8 8E BF EE DE CE BC AD BB FE 1 1 2 2 2 3 3 2 2 1 2 2 1 1 2 2 3 3 2 2 1 1 1 2 2 3 2 2 3 1 1 2 1 1 1 1 1 1 1 2 2 1 1
OPERATION
Interrupt end Subroutine end A = A - op - C E E E E E E E op.bit = 1 E C=1 G=1 op = A E E E E E E op = A, X=X+1 CPU, OSC stop op = X E E op = Y E E X= A Y=A Test dp = 0 or not X = SP A=X SP = X A=Y A e X A e Y A7-4 A3-0 A e op E E X e Y
Flag MVG HIZC
(restored) ........ N N N N N N N N V V V V V V V V . . . . . . . . . . . . . . . . H H H H H H H H . . . . . . . . Z Z Z Z Z Z Z Z C C C C C C C C
........ ........ .......1 . . 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
........ ........ ........ ........ ........ ........ ........ N. . . . . Z. N. . . . . Z. N. . . . . Z. N N . N . . . . . . . . . . . . . . . . . . . . Z Z . Z . . . .
........ ........ N. . . . . Z. N. . . . . Z. N. . . . . Z. N. . . . . Z. .......
A -4
Appendix A. Instruction Set Table
Exec. Cycle
5 5 6 6 5 5 4 5/7 6/8 5/7 4/6 5 5 5 4 4 5 5 4 4 6 6 6
No.
180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202
MNEMONIC
LDYA STYA INCW DECW ADDW SUBW CMPW CBNE CBNE DBNE DBNE NOT1 OR1 OR1B AND1 AND1B EOR1 EOR1B LDC LDCB STC TCLR1 TSET1 dp dp dp dp dp dp dp dp, rel dp+X, rel dp, rel Y, rel M.bit M.bit M.bit M.bit M.bit M.bit M.bit M.bit M.bit M.bit !abs !abs
OP CODE Words
7D DD 9D BD 1D 3D 5D FD 8D AC 7B 4B 6B 6B 8B 8B AB AB CB CB EB 5C 3C 2 2 2 2 2 2 2 3 3 3 2 3 3 3 3 3 3 3 3 3 3 3 3
OPERATION
YA = (dp+1)(dp) (dp+1)(dp) = YA (dp+1)(dp)++ (dp+1)(dp)-YA + (dp+1)(dp) YA - (dp+1)(dp) CP YA, (dp+1)(dp) if (op !=A) then branch Dec op, if (Z=0) then branch M.bit = M.bit C = M.bit : C C = (M.bit) : C C = M.bit & C C = (M.bit) & C C= M.bit + C C = (M.bit) + C C = M.bit C = (M.bit) M.bit = C !abs = A & !abs !abs = A : !abs N . N N N N N
Flag MVG HIZC
. . . . V V . . . . . . . . . . . . . . . .. .. .. .. H. H. .. Z . Z Z Z Z Z . . . . C C C
........ ........ ........ ........ ........ .......C .......C .......C .......C .......C .......C .......C .......C ........ N. . . . . Z . N. . . . . Z .
A -5
OVERVIEW FUNCTION DESCRIPTION I/O PORT PERIPHERAL HARDWARE INTERRUPT STANDBY FUNCTION RESET FUNCTION APPENDIX A. APPENDIX B.
1 2 3 4 5 6 7 8 9
Appendix B. PROGRAMMERS GUIDE
APPENDIX B. General Circuit Diagram of GMS810series.
VCC
1 R13 2 R12 3 R11 4 R10 5 VDD
R14 24 R15 23 R16 22 R17 21 REMOUT 20
Infrared LED
4MHz
OSC
6 Xout 7 Xin 8 R00 9 R01 10 R02
RESET 19 TEST 18
0.1uF
TR1
vcc
VCC
Normally use the above 100uF capacitor for prevent power drop during pulse is transmitted. If you use the SRAM back-up, use at least 220uF
VCC
Indicator LED
11 R03 12 R20
0.1uF
R05 15 R04 14 VSS 13
220uF
KEY MATRIX
GMS 81016
R07 17 R06 16
Filter for Vcc-GND noise
DC3V
We recommend to use ALKALINE battery.
GND
R11
49 50 51 = KEY 52 53 54 55 B-1 Circuit Diagram
B -1
56
R16
41 42 43 44 45 46 47 48
R15
33 25 34 26 35 27 36 28 37 29 38 30 39 31 40 32
R14
R13
R12
R10
17 18 19 20 21 22 23 24
9 10 11 12 13 14 15 16
1 2 3 4 5 6 7 8
R00 R01 R02 R03 R04 R05 R06 R07
Appendix B. PROGRAMMERS GUIDE
Mask Option List Example Refer to Circuit B-1
GMS810 MASK OPTION LIST
Code Name : GMS81016 - UAxxx 1. Device & Package GMS81004 GMS81008 GMS81016 20PIN : SOP 24PIN : SOP 28PIN : SOP 44PIN : PLCC - R0 PORT
Port Y/N Y/N R00 R01 R02 R03 R04 R05 R06
HYUNDAI ELCTRONICS Co., Ltd. MCU Application Team. Please enter check marks as
GMS81024 GMS81032 PDIP Skinny DIP Skinny DIP
B-1 ,Circuit Description: device : GMS81016 package : 24PIN SOP port R0x : All input port with pull-up resistor port R1x : All output port with N-MOS Open drain port R20 : LED Drive port
2. Inclusion of Pull up Resistor
Y : Yes N : No
R07
y
*0
y
y
y
y
y
y
y
Y : Yes N : No
- R1 PORT
Port Y/N Y/N R10 R11 R12*2 R13*2 R14*2 R15*2 R16
R17
n
*0
n
n
n
n
Y : Yes N : No
n
n
n
- R2 PORT
Port Y/N Y/N R20
R21*1 R22*1 R23*1 R24*1
n
*0
< NOTICE > . *0 : is only available in Low Voltage detection Option = Y (No . 3) *1 : is not available for 20PIN & 24PIN. So, Default option is Pull-Up. . *2 : is not available for 20PIN. So, Default Option is Pull-Up.
3. Low Voltage Detection Y/N
Date Company Name Section Name Signature
: : : :
n
S/W example Refer to Circuit B-1
; Example program for Port setting. ORG 0C000H Reset : clrg ldx #0feh txsp DI ldm R2dd,#0001_1111b ldm R2,#1111_1111b ldm R1odc,#1111_1111b ldm R1dd,#1111_1111b ldm R1,#0000_0000b ldm R0dd,#0000_0000b ldm smrr0,#1111_1111b ldm smrr1,#0000_0000b ldm Ienh,#1000_0000b ldm ckctlr,#0001_1101b clr1 IRQKSCN STOP NOP ldm R1,#1111_1111b ; GMS81016 Program Start Address ; Clear G-Flag ; Stack Pointer Initialize ; Interrupt disable ; R2 direction setting,R20: Output ; R2 data setting , R20 : High,Led off ; R1 port all open drain ; R1 direction setting ,All output ; R1 data setting , all Low for key scan ; R0 direction setting ,All input ; Stop mode release by R0 ; Stop disable by R1 ; Key scan interrupt setting ; Ckctlr setting for 16mS time delay after ; release from stop mode, WDT disable. ; key scan interrupt request flag clear ; NOP instruction must to be used after ; Stop instruction
B -2
Appendix B. PROGRAMMERS GUIDE
Key Scan
- To secure the key board scanning , read the input port after minimum 60uS delay time from output port set to Low . This time delay is for the port rising time depend on the input pull-up resistor . ; program example ,See the circuit B-1 . ldm R1,#1111_1110b call delay_60uS lda R0 . .
;R10 port set to LOW ;60uS time delay routine ;R0 port Read
R0 port Read timing
R10 R11
60uS 60uS
Fig B-2 , Input with pull-up port read time method
B -3
GMS810 MASK OPTION LIST
Code Name : HYUNDAI ELECTRONICS Co., Ltd. MCU Application Team.
1. Device & Package
GMS81004 GMS81008 GMS81016
20PIN : SOP 24PIN : SOP 28PIN : SOP 44PIN : PLCC
GMS81024 GMS81032
PDIP Skinny DIP Skinny DIP
Please enter check marks as
2. Inclusion of Pull up Resistor - R0 PORT
Port Y/N Y/N
*0
R00
R01
R02
R03
R04
R05
R06
R07
Y : Yes N : No
- R1 PORT
Port Y/N Y/N
*0
R10
R11
R12*2 R13*2 R14*2 R15*2 R16
R17
Y : Yes N : No
- R2 PORT
Port Y/N Y/N
*0
R20
*1 R21 R22*1 R23*1 R24*1
Y : Yes N : No
< NOTICE > . *0 : is only available in .Low Voltage detection Option = Y ( No. 3 ) *1 : is not available for 20PIN & 24PIN. So, Default Option is Pull-Up. . *2 : is not available for 20PIN. So Default Option is Pull-Up.
3. Low Voltage Detection
Y/N
Date Section Name Signature
: : :
Company Name :
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